computer ram DDR3 vs DDR4? Why is memory a silly device? Where is DDR5?admin
ddr 4 8gb SSD OEM computer ram DDR4 has been on the market for several years computer ram， The draft for DDR5 has also been draftedcomputer ram,” Its support is already within sight of the horizon. As a BIOS practitioner, it can be said that memory initialization is the most important part of the BIOS, and it can also be said that it is the most stupid device in the computer system. This “silly” manifests itself in the fact that it is completely passive, all activities require a memory controller to direct, and there is no firmware of its own (excluding the recent NvDIMM Optane). Its stupidity is also manifested in the fact that in order to save costs and increase capacity, the core frequency has not increased for more than ten years. After all, to increase logic is to increase the circuit, pay for electricity and increase the cost; Increasing the core frequency also costs electricity and increases costs; Everything is a province that can be saved. Why is such a stupid device still able to survive in this world, and we can still endure it? I’ll start today with what DDR4 is better than DDR3, and what features of DDR5 can be expected. If you do not understand DDR before reading, you can refer to these two articles:
it can be said that DDR4 is the biggest change in the DDR series since it was born from SDRAM. Why? If we look at the evolution of DDR3 and its predecessors:
note that the core frequency of the DRAM marked in my red box is basically unchanged, and the increase in transmission speed is achieved by increasing the number of bits of prefetch (yellow box). For example, the same is the core frequency of 100MHz, SDRAM takes once a cycle, and the speed of it and the memory controller is 100M T/s (here T is the meaning of transmission); The DDR rising edge is taken once on the falling edge, which is equivalent to 2 prefetches, and the Bus speed becomes 200; DDR2 becomes 4n prefetch and Bus speed becomes 400; DDR3, as such, 8n brings 800. The relationship between MT/s and bandwidth MB/s is <
p data-pid=”tfoIaUP_” > the core frequency of DDRx has been maintained at the level of 100Mhz to 266MHz, and the speed improvement of each generation is achieved by doubling the number of Prefetches. Let’s look at the comparison table of DDR2 and DDR3:
is there any benefit to
doing so? Of course, the most important thing is to reduce costs and save electricity. If you look at the structure inside the memory particles:
and the same speed as the external bus is the purple part (front end), while the large white part (back end) is operating at the core frequency, that is, 100 ~ 266HMz. Low speed brings two benefits:
1. Low frequency leakage current is small and low power consumption.
2. The process is simple and can be stacked on a large scale.
smart engineers from DDR onwards to multiply the prefetch, hat-tricks again and again, DDRx’s external bus bandwidth steadily increased, but the cost did not increase much, the best of both worlds, fantastic. Until DDR4, the story could not continue to play out.
DDR4, of course, reduces the voltage like every change of the previous generation; Added address line AX so that larger capacities can be supported. In addition to this, there was a distinctly different change, and the multiplication of prefetch stopped.
DDR4 and DDR3, only 8n prefetch, but in order to improve the bus speed of the front-end Front End, it has to be manipulated on the core frequency:
the core frequency is not hovering at 100 ~ 266HMz, directly 200 jump, to 400Mhz. Because the core frequency increases, the 8-bit prefetch does not change, and the bus speed is increased.
now I leave you with a thinking question, why can DDR3 keep improving prefetch, but DDR4 can’t? Here’s a hint, related to the Cache line and BL (Burst Length). I’ll publish the answer later, and I’m welcome to leave a comment in the comments section.
DDR4 has a huge and interesting change, which is also related to performance. That’s Bank Group:
along with Bank Group also brought two new Timings: tCCD_S and tCCD_L. CCD stands for “Column to Column Delay”. S is Short and L is Long. Each group can work individually, and a full 8n prefetch does not need to wait for another group, so it is a short layer, that is, a tCCD_S, which is generally 4. Inside the Group, a longer period of time is required at a time, which is the tCCD_L, and the tCCD_L varies from frequency to frequency.
if our data is coincidentally distributed across different groups, the Bank Group will bring a huge performance improvement. In the best case, 2 bank groups are the same as 16n prefetch boosts, and 4 bank groups are the same as 32n prefetch. If our data happens to be in a bank group and the frequency is very high, in the worst case, the bank group will not bring any benefit. With Bank interleave, we are generally between the best and the worst.
DDR4 improves performance a lot with the help of the core frequency increase and the bank group. Even compared with PC4-12800 and PC3-12800, there are many improvements in power consumption and performance.
the standard for DDR5 has not yet been announced, and it is reported that the voltage will be further reduced, which is of course due to the improvement of the chip process. In addition, the prefetch will further change from 8n prefetch to 16n prefetch.
a classmate will ask, you just said that DDR4 can not change from 8n to 16n, is a huge problem. Why is DDR5 no longer a problem? Because the agreement has not been announced, we will review this issue after it is announced.
add an Easter egg at the end, who knows what kind of memory the title image is (UDIMM / RDIMM / LPDIMM / LRDIMM / FBDIMM, etc.), why? Please leave a message, who guessed it first, will recommend it into a wonderful review.
other memory-related articles:
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